Systems and methods for LBIST testing using multiple functional subphases

ABSTRACT

Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between portions of the functional logic. Pseudorandom bit patterns are scanned into the scan chains so that they can be propagated through the functional logic following the scan chains. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of these scan chains. An LBIST controller causes functional operations in different portions of the functional logic to be performed at different times during a functional phase of a test cycle. The functional operations may be performed at a normal operating speed, while scan shift operations may be performed at a lower speed.

BACKGROUND

1. Field of the Invention

The invention relates generally to the testing of electronic circuits,and more particularly to systems and methods for controlling theexecution of LBIST test cycles to reduce the amount of power used by adevice under test.

2. Related Art

Digital devices are becoming increasingly complex. As the complexity ofthese devices increases, there are more and more chances for defectsthat may impair or impede proper operation of the devices. The testingof these devices is therefore becoming increasingly important.

Testing of a device may be important at various stages, including in thedesign of the device, in the manufacturing of the device, and in theoperation of the device. Testing at the design stage ensures that thedesign is conceptually sound. Testing during the manufacturing stage maybe performed to ensure that the timing, proper operation and performanceof the device are as expected. Finally, after the device ismanufactured, it may be necessary to test the device at normal operatingspeeds to ensure that it continues to operate properly during normalusage.

One way to test for defects in a logic circuit is a deterministicapproach. In a deterministic method, each possible input pattern isapplied at the inputs of the logic circuit, with each possible set ofstate values in the circuit. The output pattern generated by each set ofinputs and state values is then compared with the expected outputpattern to determine whether the logic circuit operated properly. If thenumber of possible input patterns and state values is high, however, thecost of deterministic testing of all the combinations is generally toohigh for this methodology to be practical. An alternative method oftesting that has a lower cost is therefore desirable.

One alternative is a non-deterministic approach in which pseudorandominput test patterns are applied to the inputs of the logic circuit. Theoutputs of the logic circuit are then compared to the outputs inresponse to the same pseudorandom input test patterns by a logic circuitthat is known to operate properly. If the outputs are the same, there isa high probability that the logic circuit being tested also operatesproperly. The more input test patterns that are applied to the logiccircuits, and the more random the input test patterns, the greater theprobability that the logic circuit under test will operate properly inresponse to any given input pattern. This non-deterministic testingapproach is typically easier and less expensive to implement than adeterministic approach.

One test mechanism that can be used to implement a deterministic testingapproach is a built-in self test (BIST). This may also be referred to asa logic built-in self test (LBIST) when applied to logic circuits. BISTand LBIST methodologies are generally considered part of a group ofmethodologies referred to as design-for-test (DFT) methodologies. DFTmethodologies impact the actual designs of the circuits that are to betested. LBIST methodologies in particular involve incorporating circuitcomponents into the design of the circuit to be tested, where theadditional circuit components are used for purposes of testing theoperation of the circuit's logic gates.

In a typical LBIST system, LBIST circuitry within a device under testincludes a plurality of scan chains interposed between levels of thefunctional logic of the device. Typically, pseudorandom patterns of bitsare generated and stored in the scan chains. This may be referred to asscanning the data into the scan chains. After a pseudorandom bit patternis scanned into a scan chain, the data is propagated through thefunctional logic to a subsequent scan chain. The data is then scannedout of the subsequent scan chain. This test cycle is typically repeatedmany times (e.g., 10,000 iterations,) with the results of each testcycle being combined in some manner with the results of the previoustest cycles. After all of the scheduled test cycles have been completed,the final result is compared to a final result generated by a devicethat is known to operate properly. Based upon this comparison, it isdetermined whether the device under test operated properly.

While this methodology is useful, it requires more power than wouldnormally be consumed by the chip/circuitry. This is because more of thecircuitry is active during testing than under typical operatingconditions. Therefore, more power must be provided to the chip. In orderto provide this power, a great deal of on-chip capacitance is required.The more capacitance that is necessary, the larger (and more expensive)the chip must be.

It would therefore be desirable to provide systems and methods forperforming LBIST testing that require less power than conventionalsystems and methods.

SUMMARY OF THE INVENTION

One or more of the problems outlined above may be solved by the variousembodiments of the invention. Broadly speaking, the invention comprisessystems and methods for performing logic built-in-self-tests (LBISTs) indigital circuits, where the LBIST circuitry is configured to propagatedata through different portions of the functional logic of the circuitsat different times.

In one embodiment, a STUMPS-type LBIST test architecture is incorporatedinto the design of a logic circuit. The LBIST components include a setof scan chains interposed between portions of the functional logic ofthe logic circuit. Pseudorandom bit patterns are scanned into the scanchains so that the pseudorandom bit patterns can be propagated throughthe functional logic following the scan chains. The resulting bitpatterns are captured in scan chains following the functional logic andthen scanned out of these scan chains. An LBIST controller causesfunctional operations in different portions of the functional logic tobe performed at different times (i.e., in different subphases of thefunctional phase.) For example, in one embodiment, the functional logicis divided into four portions, and data is propagated through only oneof the four portions at a time. As a result, during the functionalsubphases, only about one fourth of the power required in the functionalphase of a conventional LBIST system is needed.

One alternative embodiment comprises a method including performing oneor more test cycles of an LBIST system, where each test cycle includes ascan shift phase and multiple functional subphases. In each functionalsubphase, data is propagated through a different portion of thefunctional logic of the device under test. In one embodiment, operationsduring the functional subphases are performed at the normal operatingspeed (clock rate) of the device, while operations during the scan shiftphase are performed at a slower speed. In one embodiment, the functionaloperations are performed in the different portions of the functionallogic at different times by selectively providing a clock signal to thedifferent portions, thereby enabling operations in some portions anddisabling operations in others.

Another alternative embodiment comprises a system including functionallogic in a device under test interposed with a plurality of scan chains,and an LBIST controller. The LBIST controller is coupled to thefunctional logic and scan chains and is configured to cause data topropagate from the scan chains through the functional logic in afunctional phase of a test cycle. The data is propagated throughdifferent portions of the functional logic in different subphases of thefunctional phase. In one embodiment, the LBIST controller is configuredto cause the functional operations to be performed at a normal operatingspeed of the device under test, while scan shift operations areperformed at a lower speed. In one embodiment, the LBIST controller usescontrol signals to selectively enable or inhibit functional operationsin the different portions of the functional logic. A set of shiftregisters are used in one embodiment to select the portions of thefunctional logic in which to enable functional operations in eachfunctional subphase.

Yet another alternative embodiment comprises a device including an LBISTcontroller configured to selectively enable functional operations indifferent portions of a device under test at different times.

Numerous additional embodiments are also possible.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention may become apparent uponreading the following detailed description and upon reference to theaccompanying drawings.

FIG. 1 is a functional block diagram illustrating the principaloperation of a simple STUMPS LBIST system.

FIG. 2 is a diagram illustrating the phases of operation of the LBISTsystem in accordance with one embodiment.

FIG. 3 is a flow diagram illustrating the initialization of an LBISTsystem and the performance of repeating test cycles in accordance withone embodiment.

FIGS. 4A and 4B are a pair of diagrams illustrating the effect ofperforming functional operations of different blocks of the functionallogic in multiple subphases in accordance with one embodiment.

FIG. 5 is a functional block diagram illustrating an LBIST architecturethat can be used in conjunction with the testing of logic circuits inaccordance with one embodiment.

FIG. 6 is a functional block diagram illustrating the structure of anLBIST controller in accordance with one embodiment.

FIG. 7 is a functional block diagram illustrating the structure of aclock control block in accordance with one embodiment.

FIG. 8 is a timing diagram illustrating register values and signalsassociated with one embodiment.

FIG. 9 is a timing diagram illustrating register values and signalsassociated with an alternative embodiment.

FIG. 10 is a diagram illustrating an alternative structure for an LBISTsystem in accordance with one embodiment.

While the invention is subject to various modifications and alternativeforms, specific embodiments thereof are shown by way of example in thedrawings and the accompanying detailed description. It should beunderstood, however, that the drawings and detailed description are notintended to limit the invention to the particular embodiments which aredescribed. This disclosure is instead intended to cover allmodifications, equivalents and alternatives falling within the scope ofthe present invention as defined by the appended claims.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

One or more embodiments of the invention are described below. It shouldbe noted that these and any other embodiments described below areexemplary and are intended to be illustrative of the invention ratherthan limiting.

As described herein, various embodiments of the invention comprisesystems and methods for performing logic built-in-self-tests (LBISTs) indigital circuits, where different blocks of functional logic of theLBIST circuitry are tested during different portions of each test cycle.

In one embodiment, a STUMPS-type LBIST test architecture is incorporatedinto the design of a logic circuit. The LBIST components include a setof scan chains interposed between portions of the functional logic ofthe logic circuit. Pseudorandom bit patterns are scanned into the scanchains so that the pseudorandom bit patterns can be propagated throughthe functional logic following the scan chains. The resulting bitpatterns are captured in scan chains following the functional logic andthen scanned out of these scan chains.

The LBIST circuit performs functional operations in different portionsof the functional logic at different times. For example, in oneembodiment, the functional logic is divided (operationally, rather thanphysically) into four blocks, and data is propagated through only one ofthe four blocks at a time. As a result, during the functional subphases,only about one fourth of the power required in the functional phase of aconventional LBIST system is needed. (The functional logic may bedivided into different numbers of blocks, or uneven blocks, if desired.)

The various embodiments of the invention may provide a number ofadvantages over conventional systems. For example, the power consumed bythe circuit under test during the functional phase of LBIST testing isreduced. This reduces the power needed to be supplied by the testingequipment, and obviates the need for more expensive testing equipment(reducing the cost of acquiring or modifying testing equipment). Thereduction in power consumption may also reduce the amount of heat to bedissipated, thus reducing such demands of the testing equipment andreducing the possibility of damaging the chip as a result of the heat.

Various embodiments of the invention will be described below. Primarily,these embodiments will focus on implementations of a STUMPS-type LBISTarchitecture which is implemented within an integrated circuit. Itshould be noted that these embodiments are intended to be illustrativerather than limiting, and alternative embodiments may be implemented inBIST architectures other than the STUMPS architecture, and may also beimplemented in circuits whose components are not strictly limited tologic components (e.g., AND gates, OR gates, and the like). Many suchvariations will be apparent to persons of ordinary skill in the art ofthe invention and are intended to be encompassed by the appended claims.

Referring to FIG. 1, a functional block diagram illustrating theprinciple of operation of a simple STUMPS LBIST system is shown. TheLBIST system is incorporated into an integrated circuit. In this figure,the functional logic of the integrated circuit includes a first portion110 and a second portion 120. Functional logic 110 is, itself, a logiccircuit having a plurality of inputs 111 and a plurality of outputs 112.Similarly, functional logic 120 forms a logic circuit having a pluralityof inputs 121 and a plurality and outputs 122. Functional logic 110 iscoupled to functional logic 120 so that, in normal operation, outputs112 of functional logic 110 serve as inputs 121 to functional logic 120.

Each of the inputs to, and outputs from, functional logic 110 and 120 iscoupled to a scan latch. The set of scan latches 131 that are coupled toinputs 111 of functional logic 110 is referred to as a scan chain. Thelatches are serially coupled together so that bits of data can beshifted through the latches of a scan chain. For example, a bit may bescanned into latch 141, then shifted into latch 142, and so on, until itreaches latch 143. More specifically, as this bit is shifted from latch141 into latch 142, a second bit is shifted into latch 141. As a bit isshifted out of each latch, another bit is shifted into the latch. Inthis manner, a series of data bits can be shifted, or scanned, into theset of latches in scan chain 131, so that each latch stores acorresponding bit. Data can likewise be scanned into the latches of scanchain 132.

Just as data can be scanned into the latches of a scan chain (e.g.,131,) data can be scanned out of the latches of a scan chain. Asdepicted in FIG. 1, the latches of scan chain 132 are coupled to theoutputs of functional logic 110. Each of these latches can store acorresponding bit that is output by functional logic 110. After theseoutput bits are stored in the latches of scan chain 132, the output databits can be shifted through the series of latches and provided as acomputed output bit stream. Data can likewise be scanned out of thelatches of scan chain 133. It should be noted that the structureillustrated in FIG. 1 does not show data being scanned into scan chain133, or data being scanned out of scan chain 131. Alternativeembodiments may be configured to scan data in and out of these scanchains.

The LBIST system of FIG. 1 operates basically as follows. Pseudorandombit patterns are generated and are scanned into the scan chains (131,132) that are coupled to the inputs of functional logic 110 and 120. Thepseudorandom bit patterns that are stored in scan chains 131 and 132 arethen propagated through the corresponding functional logic. That is, thebit pattern in scan chain 131 is propagated through functional logic110, while the bit pattern in scan chain 132 is propagated throughfunctional logic 120. Functional logic 110 and 120 process the inputsand generate a corresponding set of outputs. These outputs are captured(stored) in the scan chains (132 and 133) that are coupled to theoutputs of the functional logic. The output bit patterns stored in scanchains 132 and 133 are then scanned out of these scan chains.

Referring to FIG. 2, a diagram illustrating the phases of operation ofan LBIST system in accordance with one embodiment is shown. As depictedin this figure, operation of the LBIST system begins with aninitialization phase (210). In the initialization phase, the variouscomponents of the system are prepared for operation. This may includeresetting various components, providing a seed for the pseudorandomnumber generator, setting values in registers, and so on. Initializationphase 210 is followed by a test phase (220) consisting of a series oftest cycles (test cycle 1 through test cycle z). There may be afinalization phase (not shown in the figure) after all of the testcycles are completed.

In each test cycle (e.g., 221), there is a functional phase (e.g., 230)and a scan shift phase (e.g., 240). In the functional phase, data ispropagated from one or more of the scan chains, through the functionallogic of the device in which the LBIST system is implemented, and intoone or more other scan chains. In the scan shift phase, data is scannedinto and out of the scan chains of the LBIST system.

Because each test cycle in the embodiment depicted in FIG. 2 begins witha functional phase, it is necessary during the initialization phase togenerate a first set of pseudorandom bit patterns and to load these bitpatterns into the scan chains that are interposed between the functionallogic of the device under test. After these operations are performed,the LBIST system is ready for operation. Alternatively, if each testcycle begins with a scan shift phase, data need not be scanned into thescan chains prior to the first test cycle, but the data captured at theend of the last test cycle will need to be scanned out of the scanchains during the finalization phase.

During the functional phase, the data that was scanned into the scanchains is propagated through the functional logic of the device undertest. The functional operations in this phase may, for example, beperformed at the normal operating speed of the chip (e.g., 1 Ghz.) Afterthe data is propagated through the functional logic, the output of thefunctional logic is captured by the scan chains. As noted above, a scanchain that is positioned between successive portions of the functionallogic serves to both provide inputs to the portion that precedes thescan chain and capture the outputs of the portion that follows the scanchain. The data that is captured in the scan chains at the end of thefunctional phase is scanned out of the scan chains during the scan shiftphase. At the same time the captured data is scanned out of the scanchains, new pseudorandom bit patterns are scanned into the scan chainsto prepare for the functional phase of the next test cycle. The scanshift operations in this phase may be operated at thenormal/nominal/typical operating speed of the chip or at a differentrate (e.g., a reduced rate to reduce power consumption).

As shown in FIG. 2, the operations in functional phase 230 are performedin subphases (250, 251, 255). Each of the subphases is associated with acorresponding block of the functional logic. In one embodiment, thereare n blocks of functional logic that can be separately caused toperform the functional phase of a test cycle. In this embodiment, block0 is active during subphase 0 (250), block 1 is active during subphase 1(251), and so forth, with block n-1 active during the last subphase,subphase n-1 (255). For example, if n=4, a first block is active duringa first subphase (250), a second block is active during a secondsubphase (251), a third block is active during a third subphase, and afourth block is active during a fourth subphase (255). In anotherembodiment, there are four blocks of functional logic and two functionalsubphases, with blocks 0 and 2 active during the first subphase, andblocks 1 and 3 active during the second subphase. Other embodiments mayuse other combinations and orderings, as may be desired or necessary.

The data that was captured in the scan chains can be processed andexamined to determine whether the functional logic blocks performedcorrectly. In one embodiment, the captured data from all of the scanchains in the system is compacted and provided to a multiple inputsignature register (MISR). The compacted data is combined with dataalready stored in the MISR to produce a new signature value in the MISR.Typically, this is repeated for each of a predetermined number of testcycles (e.g., 10,000,) and the resulting signature value is comparedwith a known value generated by a good chip. If the signature valuesmatch, the device under test has functioned properly. If the signaturevalues do not match, the device under test has malfunctioned. (Althoughthe comparison is performed in this embodiment after many test cycles,it may be performed after several test cycles, or even after each testcycle, in other embodiments.

The operation of the LBIST system of one embodiment is summarized inFIG. 3. FIG. 3 is a flow diagram illustrating the initialization of thesystem (305) and the repeating test cycles 310 (including functionalphase 320 and scan shift phase 340).

Referring to FIG. 3, operation of the system begins with theinitialization of the LBIST components (block 305.) During theinitialization phase, an initial bit pattern is scanned into the scanchains. After the system is initialized, it enters a functional phase,in which data is propagated from the scan chains through the functionallogic and the resulting bit patterns are captured in the scan chains.The operations of the functional phase 320 are performed in blocks.First, data is propagated through block 0 (330), then block 1 (331), anddo on through all of the blocks of functional logic, including block n(335).

Next, the system executes the scan shift phase. In this phase, thecaptured bit patterns are scanned out of the scan chains while newpseudorandom bit patterns are scanned into the scan chains (block 340.)After the test cycle is completed, the system determines whether all ofthe predetermined number of test cycles has been completed. If not,execution of the LBIST testing will continue with a subsequent testcycle (block 350). If all of the test cycles have been performed, thetesting is finalized (block 360).

Referring to FIGS. 4A and 4B, a pair of diagrams illustrating the effectof performing functional operations of different blocks of thefunctional logic in multiple subphases are shown. FIG. 4A shows theamount of power used by an LBIST system that performs functionaloperations in all of the functional logic at the same time. It can beseen that there is a baseline amount of power that is attributable to DCleakage and clock leakage in the device under test. During theinitialization phase, the amount of power that is used is relativelyminimal. By contrast, a great deal of power is required for eachfunctional (Fcn) phase. Then, during the scan shift (PRPG Scan) phase,the required power is much lower.

It should be noted that the difference in power requirements between thefunctional and scanned phases results, in part, from the fact that it isdesirable to perform the functional operations of the functional phaseat the normal operating speed of the device under test. The operationsof the scan phase, the other hand, can be performed at a reduced speed,thereby requiring less power (and taking longer to complete.) FIGS. 4Aand 4B assume that functional operations are performed at the normaloperating speed of the device under test, and that scan shift operationsare performed at a reduced speed.

Referring to FIG. 4B, the amount of power used by an LBIST system inaccordance with one embodiment is shown. Again, there is a baselineamount of DC and clock leakage. The functional, scan shift and otheroperations are added to this baseline amount of power. It can be seenthat the power required for the initialization and scan shift phases areessentially the same as for the corresponding phases of FIG. 4A. Thepower requirements for the functional phase, however, is much lowerbecause the functional operations are performed in a series ofsubphases. As depicted in the figure, the functional phase isimplemented in four subphases, so the power is reduced to approximatelyone-fourth of the power required in FIG. 4A.

It should be noted that the embodiment depicted in FIGS. 2 and 3 allowsfor a variable number of functional blocks and corresponding subphasesthat can be implemented in a variety of ways. The following exemplaryembodiment illustrates LBIST circuitry which includes a Clock ControlBlock and a Hold Control Block. This circuitry produces gating signalsthat cyclically enable a series of blocks of functional logic.Alternative embodiments may control the execution of the functionalblocks in a different manner.

In one embodiment, the LBIST system is implemented as shown in thefunctional block diagram of FIG. 5. As depicted in FIG. 5, the STUMPSarchitecture includes an LBIST controller 510, a PLL 590, a PRPG 520, aset of scan chains 540 and a MISR 570. These LBIST components areintegrated with a logic circuit 550, which the LBIST components aredesigned to test.

It should be noted that the LBIST circuitry in this embodiment ishandled in multiple blocks. For instance, one block consists of PRPG521, scan chains 541 and 542, and MISR 571, while another block consistsof PRPG 522, scan chains 543 and 544, and MISR 572. (It should be notedthat, while the PRPG and MISR are separate for each of the blocks inthis embodiment, this is not necessarily true of other embodiments, inwhich there may be a single PRPG and a single MISR that are used for allof the blocks.) There may be any number of these blocks. Similarly,there may be additional scan chains within each of the blocks. Thedifferent blocks need not be identically configured, and may havedifferent numbers of scan chains, different amounts of functional logicbetween the scan chains, and so on. It should also be noted that asingle scan chain can serve as the initial scan chain of one block andthe final scan chain of another block.

LBIST controller 510 includes control circuitry that controls theoperation of the remainder of the LBIST components 580, including clockcontrol block 511 and hold control block 512. (For purposes of clarity,LBIST controller 510 is depicted as being coupled to LBIST components580 as a group, although the controller is typically coupled directly toeach of the components.) LBIST controller 510 provides signals to LBISTcomponents 580 to control the operation of these components. LBISTcontroller 510 therefore determines the manner in which the LBISTcircuitry is initialized, the manner in which this circuitry operates inthe functional and scan shift phases, and the manner in which thetesting implemented by the circuitry is finalized.

PRPG 520 (or each of PRPG sub-blocks 521-522) typically receives a seedvalue from LBIST controller 510 and generates a pseudorandom sequence ofbits that are loaded into scan chains 540. Each of scan chains 540comprises a series of scan latches that are configured to alternatelyshift data (the pseudorandom bit patterns or functional logic output)through the scan chains or to hold data that has been propagated throughthe functional logic.

Each of scan chains 540 is positioned before or after (interposed with)respective portions of logic circuit 550. Thus, for each portion oflogic circuit 550, there is a scan chain which precedes this portion andprovides inputs to the corresponding logic, as well as a scan chainwhich follows this portion and receives the output of the correspondinglogic. For example, one portion of logic circuit 550 may receive inputbits from scan chain 541 and provide output bits to scan chain 542.Another portion of logic circuit 550 may receive input bits from scanchain 543 and provide output bits to scan chain 544. Some of scan chains540 may serve both to provide input bits to a succeeding portion oflogic circuit 550 and to receive output bits from a preceding portion oflogic circuit 550.

After the pseudorandom bit patterns have been allowed to propagatethrough the functional components of logic circuit 550 and the resultshave been captured in scan chains 540, the contents of scan chains 540are scanned out of the scan chains (i.e., they are unloaded from thescan chains) to MISR 570 (or MISR sub-blocks 571-572).

MISR 570 updates the current value in the MISR according to the datascanned out of the scan chains (e.g., by performing a modulooperation—dividing the current value by the value received from the scanchains and retaining the remainder.) The value stored in MISR 570 canthen be compared to an expected value. If the stored value does notmatch the expected value, then one or more of the operations performedby the functional components of logic circuit 550 failed, therebyproviding an incorrect data bit in the output scan chain, which was thenpropagated to MISR 570.

One of the functions of LBIST controller 510 is to generate the controlsignals necessary to execute the phases of operation depicted in FIG. 2(i.e., the initialization, functional subphases and scan shift phases.)The generation of these control signals is performed in one embodimentby an LBIST controller as depicted in FIG. 6

Referring to FIG. 6, a functional block diagram illustrating thestructure of the LBIST controller in accordance with one embodiment isshown. In particular, FIG. 6 shows the detail of hold control block 512.FIG. 7, which will be described below, shows the detail of clock controlblock 511.

As shown in FIG. 6, clock control block 511 generates four signals thatare provided to hold control block 512. The signals are the FUNC_HOLD,SCAN_HOLD, INIT and SHIFT_CLOCK signals. The INIT signal is asserted toinitialize hold control block 512. The FUNC_HOLD signal is used toassert a set of separate target signals (TARG0, TARG1, . . . ) thatenable or inhibit the LBIST circuitry for the different blocks offunctional logic within the device under test. The SCAN_HOLD signal isused to enable or inhibit the clock signal from PLL 590 to the PRPG andMISR circuitry. The SHIFT_CLOCK signal is used to shift the states ofthe target signals produced by hold control block 512.

It can be seen that hold control block 512 includes four latches(630-633,) where the output of each latch is provided to one of theinputs of a corresponding AND gate (640-643.) When the output of one ofthe latches is high and the FUNC_HOLD signal from clock control block511 is asserted, the output of the corresponding AND gate (the targetsignal) is also asserted. Each target signal is provided to one of theinputs of another corresponding AND gate (650-653.) The other inputs toeach of AND gates 650-653 is a clock signal provided by PLL 590. Thus,each target signal (TARG0-TARG3) is used to gate the clock signal fromPLL 590 to the scan chains and functional logic of the respective blockof the LBIST circuitry. In other words, if one of the target signals ishigh, the clock signal from PLL 590 is passed through the correspondingone of AND gates 650-653 to the scan chains and functional logic in theassociated portion of the LBIST circuitry.

The gating of the clock signal to the different blocks of the LBISTcircuitry is controlled by the FUNC_HOLD signal generated by clockcontrol block 511 and the values stored in shift latches 630-633. TheFUNC_HOLD signal determines when the clock signal of PLL 590 will bepassed through to the LBIST circuitry, while the values in latches630-633 determine which portion of the LBIST circuitry will receive theclock signal. If it is desired for only one of the blocks to be activeat a time during the functional phase, only one of these latches shouldhold a 1, while the others should hold 0's. If it is desired to have twoblocks of active at the same time, then two of the latches should hold1's, while the others hold 0's. These values are shifted from one latchto another in order to activate the different functional blocks duringthe different subphases of the functional phase.

The shifting of the values in latches 630-633 is accomplished throughthe use of multiplexers 620-623. Each of the multiplexers has twoinputs. One of the inputs is coupled to a corresponding one of registers610-613, while the other of the inputs is coupled to the output of apreceding one of shift latches 630-633. For example, the inputs ofmultiplexer 620 are coupled to register 610 and latch 633. When theinitialization signal from clock control block 511 (INIT) is notasserted, each multiplexer passes through the output of the precedinglatch to the input of the following latch (e.g., from the output oflatch 633 to the input of latch 630.) When the initialization signalfrom clock control block 511 (INIT) is asserted, each multiplexerselects the corresponding one of registers 610-613. These registersstore the initial values that are to be loaded into the latches when thesystem is initialized. For example, if only one block is to be activeduring each functional subphase, one of registers 610-613 will store a1, while the others store 0's. The initial values from registers 610-613or the values from the preceding latches are shifted into latches630-633 with each pulse of the SHIFT_CLOCK received from clock controlblock 511.

As described above, the clock signal of PLL 590 is provided during thefunctional subphases to alternate blocks of functional logic accordingto the target signals, TARG0-TARG3. During the scan shift phase, theFUNC_HOLD signal is not asserted, so none of the target signals isasserted, and the clock signal is not provided to any of the blocks offunctional logic. During the scan shift phase, the SCAN_HOLD signal isasserted to pass the clock signal from PLL 590 to the scan chains,PRPG(s) and MISR(s) to enable the shifting of data into and out of thescan chains. The clock signal is gated in this manner by providing theclock signal and the SCAN_HOLD signal to AND gate 655. In oneembodiment, the SCAN HOLD signal is asserted every few clock cycles(e.g., every fourth cycle) in order to reduce the rate at which data isscanned through the scan chains, and thereby reduce the power requiredby these scan operations.

Referring to FIG. 7, a functional block diagram illustrating thestructure of the clock control block in accordance with one embodimentis shown. The illustrated embodiment is configured to generate the INIT,SHIFT_CLOCK, SCAN_HOLD and FUNC_HOLD signals that are used by the holdcontrol block of FIG. 6.

The first component of clock control block 511 is a mode counter, 710.Mode counter 710 indicates the mode (functional phase or scan shiftphase) in which the LBIST circuitry is currently operating. In thisembodiment, mode counter 710 simply counts from 0 to 1, and is thenreset back to 0 (i.e., it alternates between values of 0 and 1.) Thevalue of mode counter 710 is provided to selectors 723, 733 and 743.Based upon the value stored in mode counter 710, each of these selectorsselects one of a corresponding set of registers. If mode counter 710indicates a functional phase, selector 723 selects register 721,selector 733 selects register 731, and selector 743 selects register741. If mode counter 710 indicates a scan shift phase, selector 723selects register 722, selector 733 selects register 732, and selector743 selects register 742.

Registers 721, 722, 731, 732, 741 and 742 store values that indicate thenumber of cycles to which a corresponding counter (e.g., 724 or 734)will count before a corresponding signal (e.g., INIT, SHIFT_CLOCK,FUNC_HOLD or SCAN_HOLD) is asserted. The appropriate value is selectedby the corresponding one of selectors 723, 733 and 743 and provided tothe corresponding one of comparators 725, 735 or selector 745.Comparators 725 and 735 compare the values received from the selectorswith the values of the corresponding counters and assert an outputsignal when these values match. Selector 745 selects the value of thebit indicated by the counter and provides this value as an outputsignal.

Components 721-725 are used to generate the INIT signal whichinitializes the latches of the hold control block as described in FIG.6. Register 721 stores the total number of cycles in each functionalphase (including all of the subphases) of a test cycle. Register 722stores the number of cycles that are in the scan shift phase of the testcycle. If mode counter 710 indicates the functional phase, selector 723selects the value from register 721. If mode counter 710 indicates thescan shift phase, selector 723 selects the value from register 722. Ineither case, the selected value is provided to comparator 725. Theselected value is compared to the value of cycle counter 724. When thevalue of cycle counter 724 matches the value provided by selector 723,comparator 725 asserts an output signal. This output signal is providedas the INIT signal of clock control block 511, and is also used withinthe clock control block both to reset cycle counter 724 and to incrementmode counter 710.

Components 731-736 are used to generate the SHIFT_CLOCK signal that isused to shift the values within the latches of the hold control block(see items 630-633 of FIG. 6.) Register 731 stores the number of cyclesin each functional subphase. Register 732 stores a number of cyclescorresponding to a repeating pattern of bits that that are used togenerate the FUNC_HOLD signal, as will be discussed below. If modecounter 710 indicates the functional phase (i.e., the mode counter valueis 0,) selector 733 selects the value from register 731. If mode counter710 indicates the scan shift phase (i.e., the mode counter value is 1,)selector 733 selects the value from register 732. The value selected byselector 733 is provided to comparator 735. The selected value iscompared to the value of wave counter 734, and an output signal isasserted when the value of wave counter 734 matches the value providedby selector 733. This output signal resets wave counter 734, and is alsoprovided to AND gate 736. AND gate 736 also receives the value of modecounter 710 as an input. In the functional phase (when the value of modecounter 710 is 0) and the output of comparator 735 is asserted, theSHIFT_CLOCK signal is also asserted. In the scan shift phase, the valueof mode counter 710 is 1, so the output of AND gate 736 (i.e., theSHIFT_CLOCK signal) is not asserted.

Components 741-743, 734 and 745-747 are used to generate the FUNC_HOLDand SCAN_HOLD signals that are provided to the hold control block.Registers 741 and 742 are used to store bit patterns that represent theFUNC_HOLD signal during each functional subphase and each portion of thescan shift phase. The number of bits of each value in registers 741 and742 that are used to generate the FUNC_HOLD and SCAN_HOLD signals aredetermined by the number of cycles that are counted by wave counter 734.If, for example, wave counter 734 counts three cycles in each functionalsubphase (as determined by the value in register 731,) three bits of thevalue in register 741 will be used to generate the FUNC_HOLD signal.During the scan shift phase, a different number of cycles may be countedby wave counter 734 (as determined by the value in register 732.)Selector 745 receives the value from one of registers 741 or 742 and, aswave counter 734 counts each cycle, selector 745 provides thecorresponding bit of the selected value as the FUNC_HOLD or SCAN_HOLDsignal. For instance, if the value stored in register 731 is 3, and thefirst three bits of the value in register 741 are “110”, the FUNC_HOLDsignal will be 1 during the first two cycles, then 0 during the thirdcycle, then 1 during the next two cycles, and so on. It should be notedthat AND gate 747 receives the mode counter value as an input, while ANDgate 746 receives the inverse of this value, so that only one of signalsSCAN_HOLD and FUNC_HOLD is asserted at a time.

Referring to FIG. 8, a timing diagram illustrating some of the registervalues and signals discussed above is shown. FIG. 8 corresponds to anembodiment in which there are four separately controllable blocks ofLBIST circuitry. In this embodiment, the initialization registers of thehold control block (see 610-613 of FIG. 6) store “1010”. That is, thefirst and third registers store 1's, and the second and fourth registersstore 0's. Consequently, there are two functional subphases. During onesubphase, the first and third blocks of the LBIST circuitry are active,while the second and fourth blocks are inactive. During the othersubphase, the second and fourth blocks of the LBIST circuitry areactive, and the first and third blocks are inactive.

In the embodiment of FIG. 8, the functional mode cycle register (see721) stores the value 5, while the scan shift mode cycle register (see722) stores the value 99. Thus, there are six cycles (counting from 0-5)in the functional phase 100 cycles in the scan shift phase. Thefunctional wave cycle register (see 731) stores the value 2, so thereare three cycles in each functional subphase. The scan shift wave cycleregister (see 732) stores the value 3, so the pattern of the FUNC_HOLDsignal during the scan shift phase repeats every four cycles.

The values of the mode counter (see 710,) cycle counter (see 724) andwave counter (see 734) are shown in the upper portion of FIG. 8. Whenthe value of the mode counter is 0, the LBIST circuitry is in thefunctional phase. When the mode counter is 1, the LBIST circuitry is inthe scan shift phase. During each functional phase, the cycle countercounts from 0 to 5. During each scan shift phase, the cycle countercounts from 0 to 99. During each functional subphase, the wave countercounts from 0 to 2. During each scan shift phase, the wave countercounts from 0 to 3, then returns to 0 and repeats the count from 0 to 3until the end of the scan shift phase.

When the cycle counter reaches the value of the selected mode cycleregister (5 in the functional phase and 99 in the scan shift phase,) theoutput of the comparator (725) is asserted. This increments the modecounter to change the mode (from functional to scan shift, or viceversa.) This signal is also used as the INIT signal. When this signal isasserted, the initialization registers (610-613) are reloaded into theshift registers (630-633,) to initialize their values for the nextphase.

As the wave counter counts from 0 to the value of the selected register(in this case, 2 for the functional wave cycle register and 3 for thescan shift wave cycle register,) the FUNC_HOLD signal is assertedaccording to the bits stored in the corresponding wave register (741 or742.) As depicted in FIG. 8, the functional wave register holds a valuethat begins with “110”, so the hold signal is asserted for two cyclesand then deasserted for one cycle during each functional subphase. Datais therefore propagated through the selected block(s) of the functionallogic for two cycles at the base clock rate during each functionalsubphase.

Because shift registers 630-633 initially hold the bits “1010”, signalsTARG0 and TARG2 are asserted during the first functional subphase anddata is propagated through the corresponding blocks of functional logic(while the other blocks of functional logic remain inactive.) At the endof the first subphase, comparator 735 asserts its output, resetting thewave counter and causing the SHIFT_CLOCK signal to be asserted. Theassertion of SHIFT_CLOCK causes the bits to be shifted in registers630-633, so that they hold the bits “0101”. As a result, during thesecond subphase, signals TARG1 and TARG3 are asserted, and data ispropagated through the corresponding blocks of functional logic (withthe blocks corresponding to TARG0 and TARG2 inactive.) Because only twoof the blocks of functional logic are active during each functionalsubphase, only about half of the power is required (assuming that theactive blocks are comparable to the inactive blocks.)

As shown in FIG. 8, the scan shift wave register holds a value thatbegins with “1000”, so the hold signal is asserted for one cycle andthen deasserted for three cycles, and this pattern is repeated everyfour cycles. Consequently, the hold signal is asserted every fourthcycle, causing data to be scanned into/out of the scan chains at a ratewhich is one-fourth of the base clock rate.

Referring to FIG. 9, a timing diagram illustrating an alternativescenario is shown. This scenario is based on the use of the samestructure described above in connection with FIGS. 6 and 7. In thisscenario, however, a different set of values is stored in the registers.In particular, functional mode cycle register 721 stores the value 11instead of 5, and initialization registers 610-613 store the bits“1000”.

The system operates in essentially the same manner in this scenario asin the previous scenario, except that there are four functionalsubphases (since wave counter 734 counts from 0-2 four times while cyclecounter 724 counts from 0-11.) Also, because there is only a single 1 inshift registers 630-633, only one of the four target signals(TARG0-TARG3) is active during any functional subphase. Consequently,during the functional phase, the system needs only about one-fourth ofthe power that would be required if data were propagated through all ofthe functional logic at the same time, as in conventional LBIST systems.

Still other variations on the above systems and methods are alsopossible. For example, in one alternative embodiment the structure ofthe clock control block and the hold control block are the same as inthe previous system, but the structure of the PRPG, the MISR andpossibly the scan chains is slightly different. In the system of FIG. 6,each block of the functional logic had a corresponding PRPG and MISR.Each of the blocks could therefore be activated without regard to theothers. In the alternative system however, a single PRPG and a singleMISR are used.

It should be noted that, in this alternative embodiment data ispropagated through the functional logic from right to left (as opposedto being propagated from left to right, as in FIG. 6.) This is because,in this embodiment, it is assumed that a common scan chain is usedbetween successive blocks of functional logic. In this case, afterscanning data into the scan chains, it is preferable to propagate thedata through the last block of functional logic first in order to makethe scan chain preceding this block of functional logic available tocapture the output of the preceding block of functional logic. It shouldalso be noted that the initialization registers should store the bits“1000” in order to maintain this order. This assumes that it is desiredto use the bit patterns generated by the PRPG (in order for thepropagated bits to have known characteristics.) It is alternativelypossible to simply use whatever bits propagate through one block offunctional logic as inputs to the succeeding block of functional logic.If the operation of the device under test is being compared to theidentical testing of a “good” device, the device under test shouldduplicate the results of the “good” device, even if the propagated bitpatterns are not known.

While the foregoing description presents several specific exemplaryembodiments, there may be many variations of the described features andcomponents in alternative embodiments. Many of these variations will beapparent to persons of skill in the art of the invention upon readingthe present disclosure.

Those of skill in the art will understand that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits and symbols that may be referenced throughout the abovedescription may be represented by voltages, currents, electromagneticwaves, magnetic fields and the like. The information and signals may becommunicated between components of the disclosed systems using anysuitable transport media, including wires, metallic traces, vias, andthe like.

Those of skill will further appreciate that the various illustrativelogical blocks, modules, circuits, and algorithm steps described inconnection with the embodiments disclosed herein may be implemented aselectronic hardware, computer software, or combinations of both. Toclearly illustrate this interchangeability of hardware and software,various illustrative components, blocks, modules, circuits, and stepshave been described above generally in terms of their functionality.Whether such functionality is implemented as hardware or softwaredepends upon the particular application and design constraints imposedon the overall system. Those of skill in the art may implement thedescribed functionality in varying ways for each particular application,but such implementation decisions should not be interpreted as causing adeparture from the scope of the present invention.

The various illustrative logical blocks, modules, and circuits describedin connection with the embodiments disclosed herein may be implementedor performed with application specific integrated circuits (ASICs),field programmable gate arrays (FPGAs), general purpose processors,digital signal processors (DSPs) or other logic devices, discrete gatesor transistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. A generalpurpose processor may be any conventional processor, controller,microcontroller, state machine or the like. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DSP and a microprocessor, a plurality of microprocessors, one ormore microprocessors in conjunction with a DSP core, or any other suchconfiguration.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, insoftware (program instructions) executed by a processor, or in acombination of the two. Software may reside in RAM memory, flash memory,ROM memory, EPROM memory, EEPROM memory, registers, hard disk, aremovable disk, a CD-ROM, or any other form of storage medium known inthe art. Such a storage medium containing program instructions thatembody one of the present methods is itself an alternative embodiment ofthe invention. One exemplary storage medium may be coupled to aprocessor, such that the processor can read information from, and writeinformation to, the storage medium. In the alternative, the storagemedium may be integral to the processor. The processor and the storagemedium may reside, for example, in an ASIC. The ASIC may reside in auser terminal. The processor and the storage medium may alternativelyreside as discrete components in a user terminal or other device.

The benefits and advantages which may be provided by the presentinvention have been described above with regard to specific embodiments.These benefits and advantages, and any elements or limitations that maycause them to occur or to become more pronounced are not to be construedas critical, required, or essential features of any or all of theclaims. As used herein, the terms “comprises,” “comprising,” or anyother variations thereof, are intended to be interpreted asnon-exclusively including the elements or limitations which follow thoseterms. Accordingly, a system, method, or other embodiment that comprisesa set of elements is not limited to only those elements, and may includeother elements not expressly listed or inherent to the claimedembodiment.

1. A method comprising: performing one or more test cycles of an LBISTsystem, including in each test cycle consecutively performing aplurality of functional subphases, wherein in each functional subphasedata is propagated from one or more of a plurality of scan chainsthrough a different portion of functional logic in a device under test,and performing a scan-shift phase in which data is scanned into and outof the scan chains.
 2. The method of claim 1, wherein the functionalsubphases in each test cycle are performed at a normal operating speedof the device under test.
 3. The method of claim 2, wherein the scanshift phase is performed at a speed that is less than the normaloperating speed of the device under test.
 4. The method of claim 1,further comprising providing pseudorandom bit patterns to each of thedifferent portions of functional logic from a separate pseudorandom bitpattern generator, and providing data which is propagated through eachof the different portions of functional logic to a separate multipleinput signature register.
 5. The method of claim 1, further comprisingproviding pseudorandom bit patterns to each of the different portions offunctional logic from a common pseudorandom bit pattern generator andproviding data propagated which is through each of the differentportions of functional logic to a common multiple input signatureregister.
 6. The method of claim 1, wherein performing the functionalsubphases comprises, in each functional subphase, enabling functionaloperations in one or more of the portions of functional logic andinhibiting functional operations in one or more others of the portionsof functional logic.
 7. The method of claim 6, wherein enablingfunctional operations in one or more of the portions of functional logicand inhibiting functional operations in one or more others of theportions of functional logic comprises selectively gating a clock signalto the portions of functional logic.
 8. A system comprising: functionallogic in a device under test; a plurality of scan chains interposed withthe functional logic; and an LBIST controller coupled to the functionallogic and scan chains; wherein the LBIST controller is configured topropagate data from the scan chains through each of two or moredifferent portions of the functional logic in a corresponding functionalsubphase of a test cycle; and wherein the LBIST controller is configuredto execute the functional subphases consecutively in a functional phaseand to execute the functional phase alternately with a scan shift phase.9. The system of claim 8, wherein the LBIST controller is configured tocause functional operations to be performed during the functionalsubphases at a normal operating speed of the device under test.
 10. Thesystem of claim 9, wherein the LBIST controller is configured to causescan shift operations to be performed during the scan shift phase at aspeed that is less than the normal operating speed of the device undertest.
 11. The system of claim 8, further comprising a plurality ofpseudorandom bit pattern generators and a plurality of multiple inputsignature registers, wherein each of the pseudorandom bit patterngenerators and each of the multiple input signature registers isassociated with a corresponding one of the different portions of thefunctional logic.
 12. The system of claim 8, further comprising a singlepseudorandom bit pattern generator configured to provide pseudorandombit patterns to each of the different portions of functional logic and asingle multiple input signature register configured to receive datawhich is propagated through each of the different portions of functionallogic.
 13. The system of claim 8, wherein the LBIST controller isconfigured to provide a plurality of control signals to the differentportions of the functional logic, wherein each control signalcorresponds to one of the different portions of the functional logic,and wherein each control signal alternately enables or inhibitsfunctional operations in the corresponding portion of the functionallogic.
 14. The system of claim 13, further comprising a plurality ofshift latches, wherein each shift latch corresponds to one of thecontrol signals, wherein the LBIST controller is configured to enable orinhibit each control signal based upon the contents of the correspondingshift latch, and wherein the LBIST controller is configured to shift thecontents of the shift latches serially through succeeding ones of theshift latches.
 15. The system of claim 14, wherein the shift latches areeach configured to store one bit, wherein the bit stored in each shiftlatch is AND'ed with a clock signal and the result is provided as aclock signal to the corresponding portion of the functional logic.
 16. Adevice comprising: an LBIST controller; wherein the LBIST controller isconfigured to selectively enable functional operations in differentportions of a device under test at different times wherein the LBISTcontroller is configured to generate a plurality of control signals,wherein each control signal corresponds to one of the different portionsof the device under test, and wherein the LBIST controller selectivelyinhibits clock signals that are provided to the different portions ofthe device under test using the corresponding control signals.